1. Field of the Invention
The present invention relates to noise reduction in integrated circuits and circuit assemblies, particularly combination analog and digital (mixed-signal) subsystems and mixed-signal integrated circuit chips.
2. State of the Art
Both analog and digital integrated circuits have been widely used in the electronics industry for many years. Until recently, however, integrated circuits were typically either digital or analog, but not both. Mixed-signal integration, in which analog and digital circuitry is integrated on the same chip, has only recently gained widespread use, responding to the need to find new ways to continue the trend of increasing integration density. Reducing the number of chips in a product simplifies manufacture, reduces cost and increases reliability.
Mixed-signal integration, however, presents considerable problems not present in either analog or digital integrated circuits. Notably, the noise spectrum produced by dense, high-speed digital circuits can easily interfere with high-frequency analog components. Since the waveforms transitions generated by digital circuits are, at least ideally, step transitions having (in accordance with Fourier analysis) a wide noise bandwidth, potential interference of the chip's digital signals with the chip's analog signals poses a distinct threat to circuit performance.
Generally, digital circuits switch quickly between predefined voltage levels, and consequently induce transient disturbances in signal and power lines, as well as energy radiated as electromagnetic waves. Digital circuits themselves are robust in the presence of noise from other sources. By contrast, analog circuits operate at a multiplicity of voltage levels and frequencies, and are sensitive to induced noise. A design challenge therefore becomes ensuring that digital switching noise does not create interference with analog functions.
A digital circuit switching rapidly but regularly, with edges synchronous to a master clock, will generate noise with a strong spectral component at the clock frequency. Additionally, harmonics at odd multiples of the clock frequency will be generated. If the circuit remains synchronous to a master clock, but switches on random clock edges, spectral components above and below the clock frequency will also be generated.
The prior art addresses the issue of preventing noise from reaching analog circuits, or of desensitizing the analog circuits to noise. One measure used to reduce noise interference has been to group analog I/O cells together and to place analog circuitry having critical performance requirements in the vicinity of the analog I/O cells. This solution attempts to, in effect, separate the analog and digital portions of the chip to reduce the proximity of certain analog components to digital components and hence the susceptibility of the analog components to noise from the digital components. In many systems, it is possible to arrange that the analog circuits are operated on a clocked basis, rendering them less sensitive to noise at the clock frequency. Benefits are therefore obtained if the analog circuits are clocked in phase with the digital circuits. Alternatively, the digital clock frequency may be substantially above or below the frequency band in which the analog circuits operate.
The foregoing techniques are often not fully effective, since, as previously described, the digital noise extends well above and below the clock frequency. It is then necessary to resort to potentially costly shielding techniques. Integration of the analog and digital circuits may become infeasible, requiring that they be partitioned into separate chips, with a costly overhead in packaging and connectors. There therefore remains a need for further measures to more effectively reduce digital noise in dense mixed-signal integrated circuits.